IMPLEMENTATION OF GAIN CONTROL AS IP CORE

Date

2016-05-19

Author

Karabalkan, Melike Atay
Ermis, Ercan
Oner, Mehmet

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This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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Stable output level increases the accuracy of further signal processing algorithms. So, gain control algorithms are important preprocessing steps. On the other hand, implementation of gain control algorithms vary depending on environment and performance parameters. In this case, the algorithms are required re-implementation. Re-implementation is a time consuming process especially for embedded signal processing platforms like FPGA. Implementation of signal processing algorithms as IP Cores are recommended to resolve re-design requirement. IP core is a logical block that is designed for FPGAs. By means of transportable structure, it can be applied to all systems easily. This paper presents implementation of gain control algorithms as IP Core. Introduced IP Core makes it easy to implement AGC and TVG in any conliguration. Also, it accelerates design time.

Subject Keywords

FPGA, AGC, TVG, IP Core

URI

https://hdl.handle.net/11511/66656

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Unclassified, Conference / Seminar

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Citation Formats

M. A. Karabalkan, E. Ermis, and M. Oner, “IMPLEMENTATION OF GAIN CONTROL AS IP CORE,” 2016, p. 321, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/66656.