Performance evaluation of an easy to implement PLL type symbol synchronizer

Özer, Muzaffer


Performance Evaluation of the Grid-based FastSLAM in V-RFP Using MATLAB
Azak, Salim (2018-02-24)
This paper presents a Simultaneous Localization and Mapping (SLAM) application that is developed in V-REP robot simulation program by using Grid-Based FastSLAM method. In this work, the SLAM problem in an unknown indoor environment is solved with the Pioneer 3 DX mobile robot equipped with a laser range finder. Control scripts are developed in the Lua and FastSLAM scripts using MATLAB that is linked to the simulation platform by means of the Remote API feature of the V-REP. In order to evaluate of the perfo...
Performance comparison of message passing decoding algorithms for binary and non-binary low density parity check (LDPC) codes
Uzunoğlu, Cihan; Yücel, Melek D; Department of Electrical and Electronics Engineering (2007)
In this thesis, we investigate the basics of Low-Density Parity-Check (LDPC) codes over binary and non-binary alphabets. We especially focus on the message passing decoding algorithms, which have different message definitions such as a posteriori probabilities, log-likelihood ratios and Fourier transforms of probabilities. We present the simulation results that compare the performances of small block length binary and non-binary LDPC codes, which have regular and irregular structures over GF(2),GF(4) and GF...
Performance evaluation of TCP over ATM
Tunalılar, Seçkin; Bilgen, Semih; Department of Electrical and Electronics Engineering (1998)
Performance Analysis of Faster than Symbol Rate Sampling in 1-Bit Massive MIMO Systems
Üçüncü, Ali Bulut; Yılmaz, Ali Özgür (2017-05-25)
Low resolution analog-to-digital converters (ADC) attracted much attention lately for massive multiple-input multiple-output (MIMO) communication and systems with high bandwidth. Especially, 1-bit ADCs are suitable for such systems due to their low power consumption and cost. In this study, we illustrate the benefits of using faster than symbol rate (FTSR) sampling in an uplink massive MIMO system with 1-bit ADCs in terms of symbol error rate (SER). We show that FTSR sampling provides about 4 dB signal-to-n...
Performance improvement of vlsi circuits with clock scheduling
Kapucu, Kerem; Aşkar, Murat; Department of Electrical and Electronics Engineering (2009)
Clock scheduling is studied to improve the performance of synchronous sequential circuits. The performance improvement covers the optimization of the clock frequency and the peak power consumption, separately. For clock period minimization, cycle stealing method is utilized, in which the redundant cycle time of fast combinational logic is transferred to slower logic by proper clock skew adjustment of registers. The clock scheduling system determines the minimum clock period that a synchronous sequential cir...
Citation Formats
M. Özer, “Performance evaluation of an easy to implement PLL type symbol synchronizer,” Middle East Technical University, 1987.