Date

2021-2-04

Author

Özpınar, Oğuzhan

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This thesis presents acolumn-parallel time to digital converter (TDC) integrated circuit for light detection and ranging (LIDAR)systems. The designis based on direct time-of-flight (dToF) measurement. It is designed to be used with single-photon-avalanche photodiodes (SPAD)arrays. The TDC can measure the time differences up to 1μs with 125ps precision.This TDC design consistsof four main blocks. Acounter, a phase-locked loop (PLL), a delay-locked loop (DLL), and a tapped delay line (TDL) are used togetherto implement fine timing resolution and long-rangeTDC. The counter is used to increase the time difference input range. The PLL multiplies the reference clocksignalfrequency. PLL’s voltage-controlled oscillator (VCO) is a ring oscillator thathas fourdifferential stages. The outputsof thesedifferential stages have 45-degree phase differences,and it isused to obtain better timing resolution(similar to DLL operation). The TDLis used to achieveafine timing resolution.It contains severalseries delay cells with well-defined delay times. A dedicated DLL adjusts the delay time of the cells. To have lower power consumption,the TDL hasan event-driven architecture. The design is implemented in 180nm CMOS technology. The TDC has 128 columns with 26μm pixel pitch.The least significant bit(LSB)is 125ps,and the resolution is 13bit,the maximum input range resultsin1024ns(150minthedistance). The INL and DNL of the system are+2/-1LSB at maximum. The jitter noise is 8.4ps which is well below 0.5 LSB. The sampling rate is 1MS/s. The powerconsumptionof the system (all the sub-blocks are included)is 20.5mW.

Subject Keywords

Time to digital converter (TDC), Light detection and ranging (LIDAR), Phase-locked loop (PLL), Delay –locked loop (DLL), Tapped delay line (TDL)

URI

https://hdl.handle.net/11511/89776

Collections

Graduate School of Natural and Applied Sciences, Thesis