INVESTIGATION OF NEW ARCHITECTURAL FEATURES TO SUPPORT PERFORMANCE IMPROVEMENT IN EMBEDDED PROCESSORS

Download

MSc_Thesis_Othman.pdf

Date

2022-8

Author

Othman, Ahmad

Metadata

Show full item record

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Item Usage Stats

261
views

249
downloads

Recent advances in process automation, wireless sensor networks, and machine-to-machine (M2M) interfaces have caused embedded systems to be a blooming computing segment, with significant research focus on performance and energy efficiency. The embedded systems market witnessed enormous growth over the past decades and is foreknown to be boosted in the upcoming years. It has become harder to scale CMOS technologies compared to past and get performance and energy benefits through technology and circuits. Therefore, benefits that can be obtained through architectural optimizations are even more important than before. The focus of this thesis is identification and analysis of new architectural features to potentially improve performance in embedded open-source RISC-V integer processor. Energy efficiency is ultimately enhanced as well, when such enhancements are implemented with little additional power dissipation cost. The integer core of an open-source reference (Rocketchip) processor is enhanced through new fused instructions and hardware features. Statistical data collected on the common Dhrystone and Coremark benchmarks leads to the addition of five fused instructions to the RISC-V integer Instruction-Set-Architecture (ISA), and the Rocket Chip processor organization is modified to support the new instructions. Expected performance benefits are quantified as a result of these changes as compared to the reference Rocket Chip RISC-V processor. 4.4% and 6.1% reduction in instruction count is demonstrated on 500,000 iterations of Dhrystone and 5000 iterations of Coremark benchmarks, respectively, by leveraging a particular original set of fused instructions. This results in 3.8% and 5.4% reduction in execution time for Dhrystone and Coremark benchmarks, respectively.

Subject Keywords

Processor performance, Macro-op fusion, Micro-op fusion, Integer benchmarks, Embedded systems

URI

https://hdl.handle.net/11511/101339

Collections

Northern Cyprus Campus, Thesis

Suggestions

OpenMETU
Core

A Framework for Energy based Performability models for Wireless Sensor Networks Omondi, Fredrick A.; Shah, Purav; Gemikonakli, Orhan; Ever, Enver (2015-03-27) A novel idea of alternating node operations between Active and Sleep modes in Wireless Sensor Network (WSN) has successfully been used to save node power consumption. The idea which started off as a simple implementation of a timer in most protocols has been improved over the years to dynamically change with traffic conditions and the nature of application area. Recently, use of a second low power radio transceiver to triggered Active/Sleep modes has also been made. Active/Sleep operation modes have also be...
A development tool for design and analysis of MEMS based EM energy scavengers Turkyilmaz, Serol; Külah, Haluk; Muhtaroglu, Ali (2010-12-01) This paper presents a development tool for estimating the performance of an electromagnetic (EM) vibration-to-electrical MEMS energy scavenger for low power mobile computing and wireless sensor applications. The tool takes design and excitation parameters as input, and estimates output voltage waveforms and power levels. It has been correlated against validation data, and used for early evaluation and design of new MEMS modules, which could not be optimized using off-the-shelf design packages. The tool was ...
Hardware implementation of an active feature tracker for surveillance applications Solmaz, Berkan; Akar, Gözde; Department of Electrical and Electronics Engineering (2008) The integration of image sensors and high performance processors into embedded systems enabled the development of intelligent vision systems. In this thesis, we developed an active autonomous system to be used for surveillance applications. The proposed system detects a single moving object in the field of view automatically and tracks it in a wide area by controlling the pan-tilt-zoom features of the camera. The system can also go to an alarm state to warn the user. The processing unit of the system is a T...
A cross-layer protocol for wireless sensor networks Akyildiz, Ian F.; Vuran, Mehmet C.; Akan, Ozgur B. (2006-03-24) Severe energy constraints of battery-powered sensor nodes necessitate energy-efficient communication protocols in order to fulfill application objectives of wireless sensor networks (WSN). However, the vast majority of the existing solutions are based on classical layered protocols approach. It is much more resource-efficient to have a unified scheme which melts common protocol layer functionalities into a cross-layer module for resource-constrained sensor nodes. To the best of our knowledge, to date, there...
Investigation of Alternative Array Configurations of Nanowires for Maximum Power Transmission at Optical Frequencies Karaosmanoglu, Bariscan; Satana, Hasan Aykut; Dikmen, Fatih; Ergül, Özgür Salih (2017-07-14) We present a computational analysis and comparison of nanowire arrays for efficient transmission of electromagnetic power at optical frequencies. A reliable simulation environment involving the multilevel fast multipole algorithm for fast iterative solutions of surface integral equations is used to accurately compute field intensity and power density values in the vicinity of nanowires in diverse configurations. The results demonstrate favorable properties of honeycomb structures that can provide efficient ...

Citation Formats

A. Othman, “INVESTIGATION OF NEW ARCHITECTURAL FEATURES TO SUPPORT PERFORMANCE IMPROVEMENT IN EMBEDDED PROCESSORS,” M.S. - Master of Science, Middle East Technical University, 2022.