An asynchronous system design and implementation of an FPGA

Download

index.pdf

Date

2006

Author

Ayyıldız, Nizam

Metadata

Show full item record

Item Usage Stats

268
views

83
downloads

Field Programmable Gate Arrays (FPGAs) are widely used in prototyping digital circuits. However commercial FPGAs are not very suitable for asynchronous design. Both the architecture of the FPGAs and the synthesis tools are mostly tailored to synchronous design. Therefore potential advantages of the asynchronous circuits could not be observed when they are implemented on commercial FPGAs. This is shown by designing an asynchronous arithmetic logic unit (ALU), implemented in the style of micropipelines, on the Xilinx Virtex XCV300 FPGA family. The hazard characteristics of the target FPGA have been analyzed and a methodology for selftimed asynchronous circuits has been proposed. The design methodology proposes first designing a hazard-free cell set, and then using relationally placed macros (RPMs) to keep the hazard-free behavior, and incremental design technique to combine modules in upper levels without disturbing their timing characteristics. The performance of the asynchronous ALU has been evaluated in terms of the logic slices occupied in the FPGA and data latencies, and a comparison is made with a synchronous ALU designed on the same FPGA.

Subject Keywords

Computer Engineering., Computer Hardware.

URI

http://etd.lib.metu.edu.tr/upload/12607566/index.pdf
https://hdl.handle.net/11511/16383

Collections

Graduate School of Natural and Applied Sciences, Thesis

Suggestions

OpenMETU
Core

A VERSATILE MICROCOMPUTER INTERFACE AND PERIPHERAL DEVICES - AN APPLICATION IN DEUTERIUM LAMP BACKGROUND CORRECTION GRAPHITE-FURNACE ATOMIC-ABSORPTION SPECTROMETRY GOKMEN, A; YALCIN, S (1992-01-01) A versatile interface card for Apple IIe computer and various peripheral devices are designed to control instruments which generates transient signals like in graphite furnace atomic spectrometer. The interface card consists of a multiplexed analog-to-digital converter, a digital-to-analog converter, and a timer/counter chip. The timer/counter chip with 16 built-in registers can be programmed in many modes which provides a time base for real-time measurements. A stepper motor runs under the control of ti...
Data sharing and access with a corba data distribution service implementation Dursun, Mustafa; Bilgen, Semih; Department of Electrical and Electronics Engineering (2006) Data Distribution Service (DDS) specification defines an API for Data-Centric Publish-Subscribe (DCPS) model to achieve efficient data distribution in distributed computing environments. Lack of definition of interoperability architecture in DDS specification obstructs data distribution between different and heterogeneous DDS implementations. In this thesis, DDS is implemented as a CORBA service to achieve interoperability and a QoS policy is proposed for faster data distribution with CORBA features.
An FPGA implementation of real-time electro-optic & IR image fusion Çölova, İbrahim Melih; Akar, Gözde; Department of Electrical and Electronics Engineering (2010) In this thesis, a modified 2D Discrete Cosine Transform based electro-optic and IR image fusion algorithm is proposed and implemented on an FPGA platform. The platform is a custom FPGA board which uses ALTERA Stratix III family FPGA. The algorithm is also compared with state of the art image fusion algorithms by means of an image fusion software application GUI developed in Matlab®. The proposed algorithm principally takes corresponding 4x4 pixel blocks of two images to be fused and transforms them by means...
A Cascadable Random Neural Network Chip with Reconfigurable Topology Badaroglu, Mustafa; Halıcı, Uğur; Aybay, Isik; Cerkez, Cuneyt (Oxford University Press (OUP), 2010-03-01) A digital integrated circuit (IC) is realized using the random neural network (RNN) model introduced by Gelenbe. The RNN IC employs both configurable routing and random signaling. In this paper we present the networking/routing aspects as well as the performance results of an RNN network implemented by the RNN IC. In the RNN model, each neuron accumulates arriving signals and can fire if its potential at a given instant of time is strictly positive. Firing occurs at random, the intervals between successive ...
Implementation and simulation of mc68hc11 microcontroller unit using systemc for co-design studies Tuncalı, Cumhur Erkan; Aşkar, Murat; Department of Electrical and Electronics Engineering (2007) In this thesis, co-design and co-verification of a microcontroller hardware and software using SystemC is studied. For this purpose, an MC68HC11 microcontroller unit, a test bench that contains input and output modules for the verification of microcontroller unit are implemented using SystemC programming language and a visual simulation program is developed using C# programming language in Microsoft .NET platform. SystemC is a C++ class library that is used for co-designing hardware and software of a system...

Citation Formats

N. Ayyıldız, “An asynchronous system design and implementation of an FPGA,” M.S. - Master of Science, Middle East Technical University, 2006.