Cost-effective fault tolerant routing in networks on chip

Download
2008
Adanova, Venera
Growing complexity of Systems on Chip (SoC) introduces interconnection problems. As a solution for communication bottleneck the new paradigm, Networks on Chip (NoC), has been proposed. Along with high performance and reliability, NoC brings in area and energy constraints. In this thesis we mainly concentrate on keeping communication-centric design environment fault-tolerant while considering area overhead. The previous researches suggest the adoption solution for fault-tolerance from multiprocessor architectures. However, multiprocessor architectures have excessive reliance on buffering leading to costly solutions. We propose to reconsider general router model by introducing central buffers which reduces buffer size. Besides, we offer a new fault-tolerant routing algorithm which effectively utilizes buffers at hand without additional buffers out of detriment to performance.

Suggestions

SIMULATION CONCEPTS FOR INFORMATION-SYSTEM
MOURANT, RR; Tarı, Zehra Sibel (Elsevier BV, 1993-09-01)
Recent Improvements in document image systems and their low-cost implementation on networks of microcomputers is leading to the reengineering of many information systems. We describe how document image systems can be applied to information systems. In order to compare the performance of a conventional information system with one implemented with document imaging processing capability we conducted a discrete event simulation. We modeled the conventional information system for processing graduate student ...
Parallel Scalable PDE Constrained Optimization Antenna Identification in Hyperthermia Cancer Treatment Planning
SCHENK, Olaf; Manguoğlu, Murat; CHRİSTEN, Matthias; SATHE, Madan (Springer Science and Business Media LLC, 2009-01-01)
We present a PDE-constrained optimization algorithm which is designed for parallel scalability on distributed-memory architectures with thousands of cores. The method is based on a line-search interior-point algorithm for large-scale continuous optimization, it is matrix-free in that it does not require the factorization of derivative matrices. Instead, it uses a new parallel and robust iterative linear solver on distributed-memory architectures. We will show almost linear parallel scalability results for t...
Operation assignment and capacity allocation problem in automated manufacturing systems
Bilgin, Selin; Azizoğlu, Meral (Elsevier BV, 2009-03-01)
We address an operation assignment and capacity allocation problem that arises in semiconductor industries and flexible manufacturing systems. We assume the automated machines have scarce time and tool magazine capacities and the tools are available in limited quantities. The aim is to select a subset of operations with maximum total weight. We show that the problem is NP-hard in the strong sense, develop two heuristics and a Tabu Search procedure. The results of our computational tests have revealed that o...
Metadata extraction from text in soccer domain
Göktürk, Özkan; Çiçekli, Fehime Nihan; Department of Computer Engineering (2008)
Video databases and content based retrieval in these databases have become popular with the improvements in technology. Metadata extraction techniques are used for providing data to video content. One popular metadata extraction technique for mul- timedia is information extraction from text. For some domains, it is possible to nd accompanying text with the video, such as soccer domain, movie domain and news domain. In this thesis, we present an approach of metadata extraction from match reports for soccer d...
Pipelined design approach to microprocessor architectures a partial implementation : mips pıpelined architecture on fpga
Altıniğneli, Muzaffer Can; Güran, Hasan; Department of Electrical and Electronics Engineering (2005)
This thesis demonstrate how pipelining in a RISC processor is achieved by implementing a subset of MIPS R2000 instructions on FPGA. Pipelining, which is one of the primary concepts to speed up a microprocessor is emphasized throughout this thesis. Pipelining is fundamentally invisible for high level programming language user and this work reveals the internals of microprocessor pipelining and the potential problems encountered while implementing pipelining. The comparative and quantitative flow of this thes...
Citation Formats
V. Adanova, “Cost-effective fault tolerant routing in networks on chip,” M.S. - Master of Science, Middle East Technical University, 2008.