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Cost-effective fault tolerant routing in networks on chip
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Date
2008
Author
Adanova, Venera
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Growing complexity of Systems on Chip (SoC) introduces interconnection problems. As a solution for communication bottleneck the new paradigm, Networks on Chip (NoC), has been proposed. Along with high performance and reliability, NoC brings in area and energy constraints. In this thesis we mainly concentrate on keeping communication-centric design environment fault-tolerant while considering area overhead. The previous researches suggest the adoption solution for fault-tolerance from multiprocessor architectures. However, multiprocessor architectures have excessive reliance on buffering leading to costly solutions. We propose to reconsider general router model by introducing central buffers which reduces buffer size. Besides, we offer a new fault-tolerant routing algorithm which effectively utilizes buffers at hand without additional buffers out of detriment to performance.
Subject Keywords
Computer engineering.
,
Academies and learned societies (General)
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http://etd.lib.metu.edu.tr/upload/2/12609891/index.pdf
https://hdl.handle.net/11511/18224
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Graduate School of Natural and Applied Sciences, Thesis
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V. Adanova, “Cost-effective fault tolerant routing in networks on chip,” M.S. - Master of Science, Middle East Technical University, 2008.
