Date

2010

Author

Comart, İlker

Metadata

Show full item record

Item Usage Stats

273
views

173
downloads

Cite This

This thesis presents realization of two shunt, capacitive contact RF MEMS switches and two RF MEMS SPDT switches for microwave and millimeter-wave applications, two zero-level package structures for RF MEMS switches and development trials of a BCB based zero level packaging process cycle. Two shunt, capacitive contact RF MEMS switches for 26 GHz and 12 GHz operating frequencies are designed, fabricated and consistencies between fabricated devices and designs are shown through RF measurements. For the switch design at 26 GHz and at the operating frequency, return loss in the upstate is measured to be 27.61 dB, insertion loss and isolation in the downstate is measured to be 0.21 dB and 27.16 dB, respectively. For the switch design at 12 GHz and at the operating frequency, return loss in the upstate is measured to be 38.69 dB, insertion loss and isolation in the downstate is measured to be 0.05 dB and 25.84 dB, respectively. Quite accurate circuit models have been obtained for both of the RF MEMS switches. Two RF MEMS SPDT switches, which utilize the shunt, capacitive contact switches as building blocks are designed through circuit simulations. These two designs are fabricated and their RF measurements have been completed. It is shown from circuit model simulations that, the performances of the fabricated devices and desired responses corresponded to each other. For the SPDT switch design at 26 GHz, return loss at the input port is measured to be 12 dB and insertion loss is measured to be 1.24 dB. For the SPDT switch design at 12 GHz, return loss at the input port is measured to be 5.6 dB and insertion loss is measured to be 0.49 dB. The reason behind the unexpectedly bad performances has been investigated and discovered. The bad performances were due to a common mistake in the layouts of both SPDT switches. These mistakes are corrected in the circuit models and expected performances are obtained. Two different zero-level package structures which use high-resistive Si wafers have been suggested and required design changes have been made on the RF MEMS shunt, capacitive contact switches and SPDT switches in order to minimize the package effects. For this purpose polygonal CPW transitions have been designed and integrated into the designs, followed by the necessary tunings in the switch structures for which EM and circuit simulations are utilized. For the suggested package structures to be produced, two possible process cycles have been studied. One of the process flows was based on KOH anisotropic Si etching and the other one was based on DRIE (Deep Reactive Ion Etching). Great progress has been achieved in the latter process cycle, however this process cycle still needs some more study and it could not be completed in the time required for this thesis study.

Subject Keywords

Electronics.

URI

http://etd.lib.metu.edu.tr/upload/12612420/index.pdf
https://hdl.handle.net/11511/19887

Collections

Graduate School of Natural and Applied Sciences, Thesis