VLSI implementation of low-power current-mode,cmos algorithmic analog-to-digital convertes

Download
1999
Tezel, Abdulbaki

Suggestions

VLSI implementation of a digital PN matched filter.
Altıntaş, Mustafa; Aşkar, Murat; Department of Electrical and Electronics Engineering (1996)
VLSI implementation of a microprocessor compatible 128 BIT programmable correlator.
Ungan, İsmail Enis; Department of Electrical and Electronics Engineering (1989)
VLSI implementation of FIR filters by using genetic algorithms
Öner, Mehmet; Aşkar, Murat; Department of Electrical and Electronics Engineering (2000)
Vlsirealization of 8x8-bit pipelined residue arithmetic multiplier.
Enver, Fuad; Department of Electrical and Electronics Engineering (1992)
Fpga implementation of jointly operating channel estimator and parallelized decoder
Kılcıoğlu, Çağlar; Yılmaz, Ali Özgür; Department of Electrical and Electronics Engineering (2009)
In this thesis, implementation details of a joint channel estimator and parallelized decoder structure on an FPGA-based platform is considered. Turbo decoders are used for the decoding process in this structure. However, turbo decoders introduce large decoding latencies since they operate in an iterative manner. To overcome that problem, parallelization is applied to the turbo codes and the resulting parallel decodable turbo code (PDTC) structure is employed for coding. The performance of a PDTC decoder and...
Citation Formats
A. Tezel, “VLSI implementation of low-power current-mode,cmos algorithmic analog-to-digital convertes,” Middle East Technical University, 1999.