FPGA implementation of a network-on-chip

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2011

Author

Kılınç, İsmail Özsel

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This thesis aims to design a Network-on-Chip (NoC) that performs wormhole flow control method and source routing and aims to describe the design in VHDL language and implement it on an FPGA platform. In order to satisfy the diverse needs of different network traffic, the thesis aims to design the NoC in such a way that it can be modified via a user interface, which changes the descriptions in the VHDL source code. Network topology, number of router ports, number of virtual channels, buffer size and flit size are the features of the designed NoC that can be modified. In this thesis, interfaces and operations of the blocks in the NoC are defined through block diagrams and algorithmic state machines. Verification of these blocks is performed not only on computer environment via simulations tools, but also in real world. To achieve this, source nodes generating dummy flits are also designed which communicate with our user interface via RS-232 generating flits according to the information provided by the user and monitoring the received flits from other source nodes in real-time.

Subject Keywords

Networks on a chip.

URI

http://etd.lib.metu.edu.tr/upload/12613635/index.pdf
https://hdl.handle.net/11511/20957

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Graduate School of Natural and Applied Sciences, Thesis

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Citation Formats

İ. Ö. Kılınç, “FPGA implementation of a network-on-chip,” M.S. - Master of Science, Middle East Technical University, 2011.