The Development and hardware implementation of a dynamically reconfigurable and area optimized cyclic redundancy check architecture

Download

index.pdf

Date

2013

Author

Yurt, Özcan

Metadata

Show full item record

Item Usage Stats

136
views

92
downloads

The Cyclic Redundancy Check (CRC) calculation for data communication protocols is implemented by hardware calculators in several systems due to increasing throughput requirements of data communication protocols. Furthermore CRC is employed in many small scale embedded systems with different types of data communication interfaces that are implemented on FPGA. Resource utilization of these systems is frequently a critical parameter with regards to cost. In many cases, limited logic units of an FPGA have to be used very carefully to fit the design into that platform. In this thesis, we present DAROC-Dynamically Reconfigurable and ARea Optimized CRC, which is a run-time reconfigurable and area-minimized CRC calculator. The ability of reconfiguration enables DAROC calculating different CRCs for several standards with a single instance of implementation. DAROC reaches the throughput of 705 Mbps that is sufficient for the target embedded systems with less resource consumption compared to the previous reconfigurable CRC implementations.

Subject Keywords

Data transmission systems., Polynomials., Multiplexing., Electronic circuits., Cyclic Redundancy Check., Field programmable gate arrays.

URI

http://etd.lib.metu.edu.tr/upload/12616353/index.pdf
https://hdl.handle.net/11511/23018

Collections

Graduate School of Natural and Applied Sciences, Thesis

Suggestions

OpenMETU
Core

The performance and efficiency of envelope elimination and restoration transmitters for future multiple-input multiple-output wireless local area networks Nesimoglu, T.; Parker, S. C. J.; Morris, K. A.; McGeehan, J. P. (Institution of Engineering and Technology (IET), 2008-03-01) The inefficiency of contemporary power amplifiers ( PAs), when operating in their linear region, is a major obstacle to mobile operation of wireless local area networks ( WLANs) based on IEEE 802.11n. Therefore the use of more efficient envelope elimination and restoration ( EER) transmitter architectures is considered. In addition to high efficiency it is also necessary to satisfy the spectral mask and achieve satisfactory link- level performance. Link- level simulations of a contemporary WLAN PA show that...
A low latency, high throughput and scalable hardware architecture for flow tables in software defined networks Eral, Göksan; Schmidt, Şenan Ece; Department of Electrical and Electronics Engineering (2016) Software Defined Networking (SDN) is a new paradigm which requires multi-field packet classification for each received packet by looking up Flow Tables which contain a large number of rules and corresponding actions. The rules are defined by upto 15 packet header fields including IP source and destination address. If more than one rule rule matches then the action of the highest priority rule is executed. Furthermore rules with wildcard fields are possible. The SDN Flow Table should scale with the rule coun...
A longest path problem for evaluating the worst case packet delay of switched ethernet Schmidt, Klaus Verner; Schmidt, Şenan Ece (2010-07-09) In the recent years, the use of real-time Ethernet protocols becomes more and more relevant for time-critical networked industrial applications. In this context, this paper presents a method to compute the worst-case packet delays on switched Ethernet. Based on an evaluation of the packet delays at each switch port and the network topology, we construct a weighted directed graph that allows to find the worst-case end-to-end packet delay by solving a conventional longest-path problem.
Pilot-aided packet synchronization and single-tone parameter estimation on an FPGA platform FPGA platformunda pilot dizini ekleme yöntemiyle paket senkronizasyonu ve tek ton parametre kestirimi Özel, Ömür; Vural, Mehmet; Yılmaz, Ali Özgür (2007-12-01) In this paper, an FPGA implementation in which packet synchronization is performed by transmitting pilot sequences will be explained. In addition, in order to recover the frequency offset between the frequencies of oscillators at the transmitter and the receiver, a PLL like structure is proposed.
Data sharing using mqtt and zigbee-based dds on resource-constrained contiki-based devices Yıldırım, Tunahan; Oğuztüzün, Mehmet Halit S.; Department of Computer Engineering (2020) This thesis describes the implementation of data sharing among resource-constrained IoT devices using two different middleware: MQTT(Message Queuing Telemetry Transport) and DDS (Data Distribution Services) for Real-Time Systems. In our setting, all IoT devices run under the Contiki operating system. In the configuration for DDS, a pair of Texas Instruments’ MSP430 processor-based ZigBee powered Advanticsys XM1000 device is used to realize data sharing between wireless sensor network devices without a serve...

Citation Formats

Ö. Yurt, “The Development and hardware implementation of a dynamically reconfigurable and area optimized cyclic redundancy check architecture,” M.S. - Master of Science, Middle East Technical University, 2013.