A low latency, high throughput and scalable hardware architecture for flow tables in software defined networks

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Date

2016

Author

Eral, Göksan

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Software Defined Networking (SDN) is a new paradigm which requires multi-field packet classification for each received packet by looking up Flow Tables which contain a large number of rules and corresponding actions. The rules are defined by upto 15 packet header fields including IP source and destination address. If more than one rule rule matches then the action of the highest priority rule is executed. Furthermore rules with wildcard fields are possible. The SDN Flow Table should scale with the rule count while providing high throughput supporting the Gbps network data rates. In addition, recent data center applications such as high frequency/speed trading require ultra low latency. Motivated by these requirements, this thesis proposes Fast Scalable SDN Table (FASST), a hardware architecture for a low latency, scalable and high throughput SDN Flow Table Implementation. FASST provides a high throughput up to 200 Mega-Packet-Per-Second (MPPS) while achieving a very low average latency. To this end, FASST caches the frequently accessed rules exploiting the known temporal locality in the network traffic. FASST is implemented and evaluated on real hardware using Altera Stratix-V state-of-the-art FPGA. For a network characteristics showing strong locality, FASST always achieves a lower average latency compared to recent works with a decrease of up to %97.

Subject Keywords

Computer architecture., Computer network architectures., Field programmable gate arrays.

URI

http://etd.lib.metu.edu.tr/upload/12620358/index.pdf
https://hdl.handle.net/11511/25937

Collections

Graduate School of Natural and Applied Sciences, Thesis

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Citation Formats

G. Eral, “A low latency, high throughput and scalable hardware architecture for flow tables in software defined networks,” M.S. - Master of Science, Middle East Technical University, 2016.