Show/Hide Menu
Hide/Show Apps
Logout
Türkçe
Türkçe
Search
Search
Login
Login
OpenMETU
OpenMETU
About
About
Open Science Policy
Open Science Policy
Open Access Guideline
Open Access Guideline
Postgraduate Thesis Guideline
Postgraduate Thesis Guideline
Communities & Collections
Communities & Collections
Help
Help
Frequently Asked Questions
Frequently Asked Questions
Guides
Guides
Thesis submission
Thesis submission
MS without thesis term project submission
MS without thesis term project submission
Publication submission with DOI
Publication submission with DOI
Publication submission
Publication submission
Supporting Information
Supporting Information
General Information
General Information
Copyright, Embargo and License
Copyright, Embargo and License
Contact us
Contact us
FASST: A high performance scalable rule table hardware architecture for software defined networks-FASST: Yazılım Tanımlı Bilgisayar Agları içinYüksek Ba¸sarımlı, Ölçeklenebilir bir Kural TablosuDonanım Mimarisi
Date
2018-07-09
Author
ERAL, GÖKSAN
Schmidt, Şenan Ece
Metadata
Show full item record
This work is licensed under a
Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License
.
Item Usage Stats
219
views
0
downloads
Cite This
In this paper, a new hardware architecture FASST, which can provide high performance in packet classification for SDN Rule Tables, is proposed. FASST achieves high throughput at very low packet latency using a TCAM-based parallel cache, temporal locality in the network and FPGA hardware parallelism. FASST is implemented and evaluated on Altera Stratix-V FPGA and 200 M packets/s throughput is verified functionally. FASST achieves a significantly lower average packet latency by exploiting the strong temporal locality of computer networks.
Subject Keywords
Field programmable gate arrays
,
Software
,
Hardware
,
Throughput
,
Computer architecture
,
Dogs
,
Blogs
URI
https://hdl.handle.net/11511/40589
DOI
https://doi.org/10.1109/siu.2018.8404248
Collections
Department of Electrical and Electronics Engineering, Conference / Seminar
Suggestions
OpenMETU
Core
GF (2M) multiplier implementation on a partially reconfigurable FPGA
Kocalar, Gizem; Bazlamaçcı, Cüneyt Fehmi; Department of Electrical and Electronics Engineering (2015)
The thesis aims to design and implement a Galois field multiplier IP block that adapts to changing input traffic conditions, using partial reconfiguration feature of FPGAs. Two different multiplier blocks are used for high and low traffic rates. First, an area efficient multiplier block with small area utilization and low power consumption is designed by using splitting type multiplication algorithms. Second, a high performance multiplier IP block with higher resource consumption but better time performance is d...
A low latency, high throughput and scalable hardware architecture for flow tables in software defined networks
Eral, Göksan; Schmidt, Şenan Ece; Department of Electrical and Electronics Engineering (2016)
Software Defined Networking (SDN) is a new paradigm which requires multi-field packet classification for each received packet by looking up Flow Tables which contain a large number of rules and corresponding actions. The rules are defined by upto 15 packet header fields including IP source and destination address. If more than one rule rule matches then the action of the highest priority rule is executed. Furthermore rules with wildcard fields are possible. The SDN Flow Table should scale with the rule coun...
Computational platform for predicting lifetime system reliability profiles for different structure types in a network
Akgül, Ferhat (2004-01-01)
This paper presents a computational platform for predicting the lifetime system reliability profiles for different structure types located in an existing network. The computational platform has the capability to incorporate time-variant live load and resistance models. Following a review of the theoretical basis, the overall architecture of the computational platform is described. Finally, numerical examples of three existing bridges (i.e., a steel, a prestressed concrete, and a hybrid steel-concrete bridge...
FPGA implementation of license plate detection and recognition
Sarıkavak, Serap; Bulut, Mehmet Mete; Akar, Gözde; Department of Electrical and Electronics Engineering (2013)
In this thesis, license plate detection and recognition system based on Gabor approach is proposed and recognition part of the system is implemented on the FPGA platform. The purpose of this project is to develop a system that extracts license plate region from image, taken from proposed distance, and recognizes the characters on this region. For this project, techniques on the literature are investigated and some of them are implemented. In the localization of the plate region, color space conversion, imag...
Feasibility study for dynamic context switching inpartially reconfigurable FPGAS
Yılmaz, Esat; Bazlamaçcı, Cüneyt Fehmi; Department of Electrical and Electronics Engineering (2019)
Reconfiguration of computing and control circuits according to dynamically changing needs is a supportive concept which saves design-time and the space needed for floorplanning in comparison to application specific integrated circuits (ASIC). FPGAs which are commonly used reconfigurable devices have both full and partial reconfiguration features. Dynamic partial reconfiguration is a technique which enables some part of the circuit to be reconfigured while other parts are running. This feature allows the use...
Citation Formats
IEEE
ACM
APA
CHICAGO
MLA
BibTeX
G. ERAL and Ş. E. Schmidt, “FASST: A high performance scalable rule table hardware architecture for software defined networks-FASST: Yazılım Tanımlı Bilgisayar Agları içinYüksek Ba¸sarımlı, Ölçeklenebilir bir Kural TablosuDonanım Mimarisi,” 2018, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/40589.