FASST: A high performance scalable rule table hardware architecture for software defined networks-FASST: Yazılım Tanımlı Bilgisayar Agları içinYüksek Ba¸sarımlı, Ölçeklenebilir bir Kural TablosuDonanım Mimarisi

Date

2018-07-09

Author

ERAL, GÖKSAN
Schmidt, Şenan Ece

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In this paper, a new hardware architecture FASST, which can provide high performance in packet classification for SDN Rule Tables, is proposed. FASST achieves high throughput at very low packet latency using a TCAM-based parallel cache, temporal locality in the network and FPGA hardware parallelism. FASST is implemented and evaluated on Altera Stratix-V FPGA and 200 M packets/s throughput is verified functionally. FASST achieves a significantly lower average packet latency by exploiting the strong temporal locality of computer networks.

Subject Keywords

Field programmable gate arrays, Software, Hardware, Throughput, Computer architecture, Dogs , Blogs

URI

https://hdl.handle.net/11511/40589

DOI

https://doi.org/10.1109/siu.2018.8404248

Collections

Department of Electrical and Electronics Engineering, Conference / Seminar

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Citation Formats

G. ERAL and Ş. E. Schmidt, “FASST: A high performance scalable rule table hardware architecture for software defined networks-FASST: Yazılım Tanımlı Bilgisayar Agları içinYüksek Ba¸sarımlı, Ölçeklenebilir bir Kural TablosuDonanım Mimarisi,” 2018, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/40589.