Column level two-step multi-slope analog to digital converter for CMOS image sensors

Tunca, Can
In the past few years, CMOS image sensors has performed an enormous growth in technology and their market is broadened with the integration cameras on the cell phones. The advancement trend continues as the pixel sizes getting smaller and the array formats getting larger. With pixels decreasing in size and growing in numbers, faster row read-out speed requirements have emerged to keep frame rates constant. Column parallel ADC architectures meet these demands as they utilize large numbers of parallel conversion channels. This thesis presents the design of a 12-bit column parallel Two-Step Multi-Slope (TSMS) analog to digital converter for low power CMOS image sensors. TSMS ADC architecture enables larger conversion speeds compared to widely implemented Single Slope architecture on its Two-Step Single-Slope (TSSS) mode. Proposed design can achieve even larger readout speeds in the TSMS mode, where it exploits the relaxed quantization noise requirements for larger shot noise, introduced to the circuitry by vi pixels subject to a large photon flux, by reducing the conversion resolution and increasing the conversion speed. The design is realized for pixel pitch of 6.7µm. Power consumption per column ADC is 88 µW and sampling speeds larger than 50kS/s is supported. The prototype IC generates timing and biasing signals on its own. Using SPI interface, bias voltages can be trimmed with the help of DACs and timing signals can be programmed to adapt different operation modes and speeds. Layout of the design is drawn using 180nm process and 3.15 mm × 3.15 mm sized prototype IC is sent to multi-project-wafer MPW run for fabrication.  


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Citation Formats
C. Tunca, “Column level two-step multi-slope analog to digital converter for CMOS image sensors,” M.S. - Master of Science, Middle East Technical University, 2017.