Implementation and performance of parallellised turbo decoders

Date

2011-01-04

Author

Yılmaz, Ali Özgür
Yılmaz, Ayşen

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In this study, the authors discuss the implementation of a low latency decoding algorithm for turbo codes and repeat accumulate codes and compare the implementation results in terms of maximum available clock speed, resource consumption, error correction performance and the data (information bit) rate. In order to decrease the latency a parallellised decoder structure is introduced for these mentioned codes and the results are obtained by implementing the decoders on a field programmable gate array. The memory collision problem is avoided by using collision-free interleavers. Through a proposed quantisation scheme and normalisation in forward/backward recursions, computational issues are handled for overcoming the overflow and underflow issues in a fixed point arithmetic. Also, the effect of different implementation styles are observed.

Subject Keywords

Low-power, Desıgn, Architecture

URI

https://hdl.handle.net/11511/30228

Journal

IET COMMUNICATIONS

DOI

https://doi.org/10.1049/iet-com.2009.0647

Collections

Graduate School of Natural and Applied Sciences, Article

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Citation Formats

A. Ö. Yılmaz and A. Yılmaz, “Implementation and performance of parallellised turbo decoders,” IET COMMUNICATIONS, pp. 39–50, 2011, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/30228.