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Architectural energy-delay assessment of ABACUS multiplier with respect to other multipliers

Gürdür, Didem
This study presents a logic implementation for the recently proposed ABACUS integer multiplier architecture and compares it with other fundamental multipliers. The ABACUS m x n implementation was modeled, simulated, and evaluated using the PETAM (Power Estimation Tool for Array Multipliers) tool developed during this study, against Carry Save Array Multiplier (CSAM), Ripple Carry Array Multiplier (RCAM) and Wallace Tree Multiplier (WTM) for energy-delay performance. The resulting implementation models did not provide as much value in energy-delay as the originally reported crude architectural analysis predicted, especially when the multiplier size is smaller than 32x32. This is due to the fact that threshold detection required by ABACUS “column compression” is not trivial to implement at low cost using standard logic approaches. On the other hand, the proposed logic implementation of ABACUS in this thesis is scalable to any m x n integer multiplier, and demonstrates close to 2x energy-delay product improvement potential compared to scalable RCAM and CSAM logic implementations for 64x64 bits multiplication, and more for larger multipliers.