Power-Delay Analysis of an ABACUS Parallel Integer Multiplier VLSI Implementation

Ercan, Furkan
Muhtaroglu, Ali
ABACUS parallel architecture was previously proposed as an alternate integer multiplication approach with column compression and parallel carry futures. This paper presents a VLSI implementation for ABACUS and benchmarks it against the conventional Wallace Tree Multiplier (WTM). Simulations are conducted with UMC180nm technology in Cadence environment. Although WTM implementation results in 26.6% fewer devices, ABACUS implementation has 8.6% less power dissipation with matched delay performance, due to 27.8% lower average activity.
5th International Conference on Energy Aware Computing Systems & Applications (ICEAC)


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Citation Formats
F. Ercan and A. Muhtaroglu, “Power-Delay Analysis of an ABACUS Parallel Integer Multiplier VLSI Implementation,” Cairo, Egypt, 2015, p. 0, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/65272.