Power-Delay Analysis of an ABACUS Parallel Integer Multiplier VLSI Implementation

Date

2015-03-26

Author

Ercan, Furkan
Muhtaroglu, Ali

Metadata

Show full item record

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Item Usage Stats

174
views

0
downloads

ABACUS parallel architecture was previously proposed as an alternate integer multiplication approach with column compression and parallel carry futures. This paper presents a VLSI implementation for ABACUS and benchmarks it against the conventional Wallace Tree Multiplier (WTM). Simulations are conducted with UMC180nm technology in Cadence environment. Although WTM implementation results in 26.6% fewer devices, ABACUS implementation has 8.6% less power dissipation with matched delay performance, due to 27.8% lower average activity.

Subject Keywords

Arithmetic multiplier, Power, Delay performance, Counter, Parallel multiplication, PDP

URI

https://hdl.handle.net/11511/65272

Conference Name

5th International Conference on Energy Aware Computing Systems & Applications (ICEAC)

Collections

Engineering, Conference / Seminar

Suggestions

OpenMETU
Core

HYBRID ANALYSIS OF TMVP FOR MODULAR POLYNOMIAL MULTIPLICATION IN CRYPTOGRAPHY Efe, Giray; Cenk, Murat; Department of Cryptography (2022-3-07) Polynomial multiplication on the quotient ring Z[x]/<x^n+-1> is one of the most fundamental, general-purpose operations frequently used in cryptographic algorithms. Therefore, a possible improvement over a multiplication algorithm directly affects the performance of algorithms used in a cryptographic application. Well-known multiplication algorithms such as Schoolbook, Karatsuba, and Toom-Cook are dominant choices against NTT in small and ordinary input sizes. On the other hand, how these approaches are imp...
Power-delay optimized VLSI threshold detection circuits and their use in parallel integer multiplication Ercan, Furkan; Muhtaroğlu, Ali; Sustainable Environment and Energy Systems (2015-6) Threshold detection is a fundamental logic function that has broad use in arithmetic processors, and other digital applications. Thus, any improvement in threshold detection in terms of power and/or delay contributes significantly to the field of digital circuit design. A recently reported parallel integer multiplier architecture, ABACUS, uses column compression networks to compress partial products through the final addition network. Architecture of column compression network of ABACUS is suitable for thre...
Waterfall region analysis for iterative decoding Yılmaz, Ali Özgür (2004-12-01) Finite length analysis of iterative decoders can be done by using probabilistic models based on EXIT charts. The validity of these models will be investigated by checking the performance of iterative decoding under various scenarios.
Parallel implementation of a gas-kinetic BGK method on unstructured grids for 3-D inviscid missile flows Ilgaz, Murat; Tuncer, İsmail Hakkı (2009-10-12) A 3-D gas-kinetic BGK method and its parallel solution algorithm are developed for the computation of inviscid missile flows on unstructured grids. Flow solutions over a supersonic missile are presented to validate the accuracy and robustness of the method. It is shown that the computation time, which is an important deficiency of gas-kinetic BGK methods, may significantly be reduced by performing computations in parallel. © 2009 Springer-Verlag Berlin Heidelberg.
Efficient subquadratic space complexity binary polynomial multipliers based on block recombination Cenk, Murat; Negre, Christophe (2014-09-01) Some applications like cryptography involve a large number of multiplications of binary polynomial. In this paper we consider two, three and four-way methods for parallel implementation of binary polynomial multiplication. We propose optimized three and four-way split formulas which reduce the space and time complexity of the best known methods. Moreover, we present a block recombination method which provides some further reduction in the space complexity of the considered two, three and four-way split mult...

Citation Formats

F. Ercan and A. Muhtaroglu, “Power-Delay Analysis of an ABACUS Parallel Integer Multiplier VLSI Implementation,” Cairo, Egypt, 2015, p. 0, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/65272.