GF (2M) multiplier implementation on a partially reconfigurable FPGA

Download
index.pdf
2015
Kocalar, Gizem
Show full item record
204
views
193
downloads
The thesis aims to design and implement a Galois field multiplier IP block that adapts to changing input traffic conditions, using partial reconfiguration feature of FPGAs. Two different multiplier blocks are used for high and low traffic rates. First, an area efficient multiplier block with small area utilization and low power consumption is designed by using splitting type multiplication algorithms. Second, a high performance multiplier IP block with higher resource consumption but better time performance is designed. At low traffic rates, area efficient multiplier block is used for better area and power utilization. However, when multiplication requests exceed a certain threshold, area efficient multiplier is not capable of serving the incoming requests within an acceptabletime. In such cases, the high performance multiplier is activated by reconfiguring the FPGA using a partial bit file to be able to serve the multiplication requests faster. Although power consumption of high performance multiplier is high, on average it is balanced by use of area efficient multiplier when throughput requirement is variable.
Galois field., Field programmable gate arrays., Data encryption (Computer science).
http://etd.lib.metu.edu.tr/upload/12618771/index.pdf
https://hdl.handle.net/11511/24660
Graduate School of Natural and Applied Sciences, Thesis

Suggestions

Feasibility study for dynamic context switching inpartially reconfigurable FPGAS
Yılmaz, Esat; Bazlamaçcı, Cüneyt Fehmi; Department of Electrical and Electronics Engineering (2019)
Reconfiguration of computing and control circuits according to dynamically changing needs is a supportive concept which saves design-time and the space needed for floorplanning in comparison to application specific integrated circuits (ASIC). FPGAs which are commonly used reconfigurable devices have both full and partial reconfiguration features. Dynamic partial reconfiguration is a technique which enables some part of the circuit to be reconfigured while other parts are running. This feature allows the use...
FASST: A high performance scalable rule table hardware architecture for software defined networks-FASST: Yazılım Tanımlı Bilgisayar Agları içinYüksek Ba¸sarımlı, Ölçeklenebilir bir Kural TablosuDonanım Mimarisi
ERAL, GÖKSAN; Schmidt, Şenan Ece (2018-07-09)
In this paper, a new hardware architecture FASST, which can provide high performance in packet classification for SDN Rule Tables, is proposed. FASST achieves high throughput at very low packet latency using a TCAM-based parallel cache, temporal locality in the network and FPGA hardware parallelism. FASST is implemented and evaluated on Altera Stratix-V FPGA and 200 M packets/s throughput is verified functionally. FASST achieves a significantly lower average packet latency by exploiting the strong temporal ...
Computational platform for predicting lifetime system reliability profiles for different structure types in a network
Akgül, Ferhat (2004-01-01)
This paper presents a computational platform for predicting the lifetime system reliability profiles for different structure types located in an existing network. The computational platform has the capability to incorporate time-variant live load and resistance models. Following a review of the theoretical basis, the overall architecture of the computational platform is described. Finally, numerical examples of three existing bridges (i.e., a steel, a prestressed concrete, and a hybrid steel-concrete bridge...
FGPA based cryptography computation platform and the basis conversion in composite finite fields
Sial, Muhammad Riaz; Akyıldız, Ersan; Department of Cryptography (2013)
In the study of this thesis work we focused on the hardware based cryptographic algorithms computation platform, especially for elliptic-curve and hyper-elliptic curve based protocols. We worked for making the hyperelliptic curve based Tate Pairing computation efficient specially for hardware implementations. To achieve this one needs to make the underlying finite field arithmetic implementations efficient. For this we study the finite fields of type $\mathbb{F}_q, q=p^{2pn}$ from the efficient implementati...
Dissimilarity maximization method for real-time routing of parts in random flexible manufacturing systems
Saygin, C; Kilic, SE (Springer Science and Business Media LLC, 2004-04-01)
This paper presents a dissimilarity maximization method (DMM) for real-time routing selection and compares it via simulation with typical priority rules commonly used in scheduling and control of flexible manufacturing systems (FMSs). DMM aims to reduce the congestion in the system by selecting a routing for each part among its alternative routings such that the overall dissimilarity among the selected routings is maximized. In order to evaluate the performance of DMM, a random FMS, where the product mix is...
Citation Formats
G. Kocalar, “GF (2M) multiplier implementation on a partially reconfigurable FPGA,” M.S. - Master of Science, Middle East Technical University, 2015.
METU IIS - Integrated Information Service open@metu.edu.tr