GF (2M) multiplier implementation on a partially reconfigurable FPGA

Kocalar, Gizem
The thesis aims to design and implement a Galois field multiplier IP block that adapts to changing input traffic conditions, using partial reconfiguration feature of FPGAs. Two different multiplier blocks are used for high and low traffic rates. First, an area efficient multiplier block with small area utilization and low power consumption is designed by using splitting type multiplication algorithms. Second, a high performance multiplier IP block with higher resource consumption but better time performance is designed. At low traffic rates, area efficient multiplier block is used for better area and power utilization. However, when multiplication requests exceed a certain threshold, area efficient multiplier is not capable of serving the incoming requests within an acceptabletime. In such cases, the high performance multiplier is activated by reconfiguring the FPGA using a partial bit file to be able to serve the multiplication requests faster. Although power consumption of high performance multiplier is high, on average it is balanced by use of area efficient multiplier when throughput requirement is variable.


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Citation Formats
G. Kocalar, “GF (2M) multiplier implementation on a partially reconfigurable FPGA,” M.S. - Master of Science, Middle East Technical University, 2015.