Feasibility study for dynamic context switching inpartially reconfigurable FPGAS

Download
2019
Yılmaz, Esat
Reconfiguration of computing and control circuits according to dynamically changing needs is a supportive concept which saves design-time and the space needed for floorplanning in comparison to application specific integrated circuits (ASIC). FPGAs which are commonly used reconfigurable devices have both full and partial reconfiguration features. Dynamic partial reconfiguration is a technique which enables some part of the circuit to be reconfigured while other parts are running. This feature allows the user to switch between different and successive tasks working in a particular block of an FPGA device. Preemption of a task might also be needed in dynamically running circuits for real-time/time-critical application requirements. Preemption requires that all current state information of the circuit is saved somewhere else before running another circuit and to run the previously saved circuit where it was stopped from. This thesis study investigates the feasibility of dynamic context switching in modernday FPGAs. For this, a reconfigurable System-on-Chip (SoC) architecture is examined. Xilinx Zynq SoC is used and AXI4-based partially reconfigurable block structure is implemented. By using DMA, readback and reconfiguration structures are implemented. DDR memory is used to store bitstream files when a partial bitstream file is downloaded to the FPGA. The resulting system designed helps to reduce required resources for big size circuits by providing and enabling a context-save and context-restore mechanism for time-critical tasks with considerably low overhead.

Suggestions

GF (2M) multiplier implementation on a partially reconfigurable FPGA
Kocalar, Gizem; Bazlamaçcı, Cüneyt Fehmi; Department of Electrical and Electronics Engineering (2015)
The thesis aims to design and implement a Galois field multiplier IP block that adapts to changing input traffic conditions, using partial reconfiguration feature of FPGAs. Two different multiplier blocks are used for high and low traffic rates. First, an area efficient multiplier block with small area utilization and low power consumption is designed by using splitting type multiplication algorithms. Second, a high performance multiplier IP block with higher resource consumption but better time performance is d...
DESIGN, IMPLEMENTATION AND VERIFICATION OF A HIGH-SPEED ON-CHIP PACKET SWITCH
YILDIZ, Ayhan Sefa; Schmidt, Şenan Ece; Department of Electrical and Electronics Engineering (2022-2-9)
In this thesis, an on-chip packet switch architecture to interconnect modules on System on Chip (SoC) platforms at high line speeds is proposed. The particular target application for the proposed on-chip switch is hardware accelerated cloud computing systems. To this end, FPGA Accelerator Cards (FAC) are employed in heterogeneous cloud data centers which implement hardware accelerators on the FPGA. The data from the cloud user is brought on the accelerators and delivered after processing through high-speed ...
Real-time hardware-in-the-loop simulation of electrical machine systems using FPGAs
Üşenme, Serdar; Dilan, R.A.; Dölen, Melik; Koku, Ahmet Buğra (2009-11-18)
This study focuses on the development an integrated software and hardware platform that is capable of performing real-time simulation of dynamic systems, including electrical machinery, for the purpose of hardware-in-the-loop simulation (HILS). The system to be controlled is first defined using a block diagram editor. The defined model is then compiled and downloaded onto an FPGA (¿Field Programmable Gate Array¿) based hardware platform, which is to interface with the controller under test and carry out the...
Computational platform for predicting lifetime system reliability profiles for different structure types in a network
Akgül, Ferhat (2004-01-01)
This paper presents a computational platform for predicting the lifetime system reliability profiles for different structure types located in an existing network. The computational platform has the capability to incorporate time-variant live load and resistance models. Following a review of the theoretical basis, the overall architecture of the computational platform is described. Finally, numerical examples of three existing bridges (i.e., a steel, a prestressed concrete, and a hybrid steel-concrete bridge...
FASST: A high performance scalable rule table hardware architecture for software defined networks-FASST: Yazılım Tanımlı Bilgisayar Agları içinYüksek Ba¸sarımlı, Ölçeklenebilir bir Kural TablosuDonanım Mimarisi
ERAL, GÖKSAN; Schmidt, Şenan Ece (2018-07-09)
In this paper, a new hardware architecture FASST, which can provide high performance in packet classification for SDN Rule Tables, is proposed. FASST achieves high throughput at very low packet latency using a TCAM-based parallel cache, temporal locality in the network and FPGA hardware parallelism. FASST is implemented and evaluated on Altera Stratix-V FPGA and 200 M packets/s throughput is verified functionally. FASST achieves a significantly lower average packet latency by exploiting the strong temporal ...
Citation Formats
E. Yılmaz, “Feasibility study for dynamic context switching inpartially reconfigurable FPGAS,” Thesis (M.S.) -- Graduate School of Natural and Applied Sciences. Electrical and Electronics Engineering., Middle East Technical University, 2019.