A Low-power analog-to-digital converter integrated circuit for data acquisition applications

Download

index.pdf

Date

2016

Author

Koçak, Serhat

Metadata

Show full item record

Item Usage Stats

248
views

143
downloads

Data acquisition systems have been used in different kinds of applications such as sensing applications, wireless communication, and healthcare. Each of these applications requires a different and unique system in order to achieve high quality acquisition. These different and unique systems employ various components such as analog-to-digital converters, digital-to-analog converters, and external electronics. Each of these components offers an optimal solution in order to satisfy the system requirements. Analog-to-digital converters known as ADCs are the main devices in the data acquisition systems which interface between the physical parameters and digital systems. Low power and high performance ADCs are preferable, since the systems are comprised of many components which lead to significant amount of power consumption. This thesis presents the design, and implementation of an analog-to-digital integrated circuit for low power data acquisition applications. 0.35 μm CMOS technology is used in order to implement the proposed ADC. In this thesis, different ADC topologies are investigated, and successive approximation register known as SAR ADC is chosen since, that structure which is low noise, dissipates low power at medium resolution, and medium speed. In this work, each part of the ADC is analyzed in order to design an optimal ADC structure. Low power solutions for the differential rail to rail comparator and digital-to-analog converter are proposed for high performance ADC. A flexible and programmable digital controller which consists of the successive approximation register is implemented in order to perform the binary search algorithm. An output serializer is employed in order to reduce the number of pads. A programmable bias generator is designed to provide bias currents to the analog blocks. The designed chip occupies 2mmx2mm silicon area, and the power dissipation of the core of the designed chip is less than 1 mW which is suitable for low power data acquisition applications. The performance of the SAR ADC is evaluated based on the simulation results which conclude that, the designed SAR ADC is a promising solution for the low power data acquisition applications. A compact test setup including a compact PCB card, a FPGA card and a PC is designed for performing the ADC characterization tests.

Subject Keywords

Low voltage integrated circuits., Analog-to-digital converters., Digital-to-analog converters., Integrated circuits., Digital electronics.

URI

http://etd.lib.metu.edu.tr/upload/12619740/index.pdf
https://hdl.handle.net/11511/25435

Collections

Graduate School of Natural and Applied Sciences, Thesis

Suggestions

OpenMETU
Core

A successive approximation register analog-to-digital converter for low-cost microbolometers Mahsereci, Yiğit Uygar; Akın, Tayfun; Eminoğlu, Selim; Department of Electrical and Electronics Engineering (2012) Commercialization of infrared (IR) vision is of vital importance for many applications, such as automobile and health care. The main obstacle in front of the further spread of this technology is the high price. The cost reduction is achieved by placing on-chip electronics and diminishing the camera size, where one of the important components is the analog-to-digital converter (ADC). This thesis reports the design of a successive approximation register (SAR) ADC for low-cost microbolometers and its test elec...
A Low-power memory CMOS integrated circuit for image sensors Üstündağ, Mithat Cem Boreyda; Akın, Tayfun; Department of Electrical and Electronics Engineering (2015) This thesis presents a low power SRAM block implemented in a 0.35 μm CMOS technology for imaging applications to be used inside a digital image processor ASIC (Application Specific Integrated Circuit). The SRAM structure is designed to be fast enough to store all the image data fed by a large format readout circuitry such as VGA (640x512), while requiring low power consumption. The low power consumption is a very critical requirement of such circuit, as the circuit will eventually be used in an embedded pla...
A Digitally programmable application specific integrated circuit for drive and data acquisition of imaging sensorsMethod of moments analysis of slotted waveguide antenna arrays Bayhan, Nusret; Akın, Tayfun; Eminoğlu, Selim; Department of Electrical and Electronics Engineering (2014) This thesis explains the implementation of a digital programmable Application Specific Integrated Circuit (ASIC) designed for imaging applications. The primary function of this ASIC is to drive imaging sensors and to do basic processing on the digital video data coming from the sensors. The ASIC is designed to handle the communication between the imaging sensor and the system. Using command based high-level instructions, this two-way communication is simplified. The ASIC can also be used to store and update...
A generic framework for optimizing performance metrics by tuning parameters of clustering protocols in WSNs Alchihabi, Abdullah; Dervis, Ates; Ever, Enver; Al-Turjman, Fadi;( Abstracts: Wireless sensor network (WSN) is a key technology trend in emerging internet of things paradigms which are commonly used for application areas such as smart-cities, smart-grids, wearables, and connected health. There is a wealth of literature which considers various cluster-based routing protocols such as LEACH, HEED, and UHEED where these protocols are compared in terms of the network lifetime and/or the total number of packets successfully received by the base station under various operational conditions. While existing studies present various approaches to form WSN clusters in the most efficient way, various parameters are manually-assigned their values such as the radius of the cluster, the number of nodes in the cluster, and the number of clusters that should be formed to reach the base station. The choice of correct parameters is essential for reaching the most efficient configuration, however existing studies do not specify a systematic way for tuning these parameters. In other words, the optimization of cluster-based WSNs through fine tuning of related system parameters is not considered in the existing studies. We believe that presenting a generic approach to tune the parameters of clustering algorithms in order to optimize the performance metrics of WSNs is a significant contribution. In this study a systematic and an efficient method is presented to tune the parameters of clustering and routing protocols. Instead of brute force, or trial and error approaches, simulated annealing and K-beams algorithms are adopted together with discrete event system simulator OMNET++ with Castalia Framework. Results are presented comparatively with brute force approach in order to show the efficiency of the new approach in finding the optimum configuration in terms of energy efficiency as well as the rate of successfully received packets.; 2019-04-01) Wireless sensor network (WSN) is a key technology trend in emerging internet of things paradigms which are commonly used for application areas such as smart-cities, smart-grids, wearables, and connected health. There is a wealth of literature which considers various cluster-based routing protocols such as LEACH, HEED, and UHEED where these protocols are compared in terms of the network lifetime and/or the total number of packets successfully received by the base station under various operational conditions....
An Implantable Multichannel Digital Neural Recording System for a Micromachined Sieve Electrode Akın, Tayfun; Bradley, R.M. (1995-06-29) This paper reports the development of an implantable, fully integrated, single-chip, multichannel neural recording system, which is powered and communicated with using an RF telemetry link. The system allows recording of /spl plusmn/500/spl mu/V neural signals from axons regenerated through a micromachined silicon sieve electrode. These signals are amplified using on-chip 100Hz to 3.IkHz bandlimited amplifiers, multiplexed, and digitized with a low-power, high speed current-mode 8-bit ADC, and then transmit...

Citation Formats

S. Koçak, “A Low-power analog-to-digital converter integrated circuit for data acquisition applications,” M.S. - Master of Science, Middle East Technical University, 2016.