MIPS Extension for a TCAM Based Parallel Architecture for Fast IP Lookup

This paper discusses the feasibility of the use of minimum independent prefix set (MIPS) algorithm in a ternary content addressable memory (TCAM) based parallel architecture proposed for high speed packet switching. MIPS algorithm is proposed earlier to transform a forwarding table into one that contains the minimum independent prefix set. In this paper we propose MIPS algorithm to be integrated into a TCAM based parallel IP lookup engine. We first analyze the table compression performance of the MIPS algorithm and demonstrate that it may lead to routing table expansion rather than compression in general. For certain cases on the other hand, MIPS algorithm performs well and is suitable to be used in TCAM based parallel IP lookup engine. We demonstrate that with the adoption of the MIPS algorithm, the overall performance, in terms of throughput, of the IP lookup engine can be enhanced considerably.
24th International Symposium on Computer and Information Sciences


Complexity reduction in radial basis function (RBF) networks by using radial B-spline functions
Saranlı, Afşar; Baykal, Buyurman (1998-01-01)
In this paper, new basis consisting of radial cubic and quadratic B-spline functions are introduced together with the CORDIC algorithm, within the context of RBF networks as a means of reducing computational complexity in real-time signal-processing applications. The new basis are compared with two other existing and popularly used basis families, namely the Gaussian functions and the inverse multiquadratic functions (IVMQ) in terms of approximation performance and computational requirements. The new basis ...
GF (2M) multiplier implementation on a partially reconfigurable FPGA
Kocalar, Gizem; Bazlamaçcı, Cüneyt Fehmi; Department of Electrical and Electronics Engineering (2015)
The thesis aims to design and implement a Galois field multiplier IP block that adapts to changing input traffic conditions, using partial reconfiguration feature of FPGAs. Two different multiplier blocks are used for high and low traffic rates. First, an area efficient multiplier block with small area utilization and low power consumption is designed by using splitting type multiplication algorithms. Second, a high performance multiplier IP block with higher resource consumption but better time performance is d...
MIMO Communication Systems Using Hierarchical Modulation
Ugur, Yigit; Yılmaz, Ali Özgür (2014-04-25)
This paper considers multiple-input multiple-output (MIMO) communication systems using hierarchical modulation. The disadvantage of the maximum-likelihood (ML) receiver is that the computational complexity increases exponentially with the number of transmit antennas and the number of bits per modulation symbol. Using MIMO communication system with 16-ary hierarchical quadrature amplitude modulation (16-HQAM), we propose a receiver structure which can be an alternative to maximum-likelihood (ML) receiver. 16...
CBFEM-MPI: A Parallelized Version of Characteristic Basis Finite Element Method for Extraction of 3-D Interconnect Capacitances
Ozgun, Ozlem; Mittra, Raj; Kuzuoğlu, Mustafa (Institute of Electrical and Electronics Engineers (IEEE), 2009-02-01)
In this paper, we present a novel, non-iterative domain decomposition method, which has been parallelized by using the message passing interface (MPI) library, and used to efficiently extract the capacitance matrixes of 3-D interconnect structures, by employing characteristic basis functions (CBFs) in the context of the finite element method (FEM). In this method, which is Failed CBFEM-MPI, the computational domain is partitioned into a number of nonoverlapping subdomains in which the CBFs are constructed b...
VSC-Based D-STATCOM With Selective Harmonic Elimination
Cetin, Alper; Ermiş, Muammer (2009-05-01)
This paper describes the design, implementation, and performance of a medium-size distribution-type static synchronous compensator (D-STATCOM) with the simplest two-level three-leg voltage-source converter (VSC) topology. Reactive-power control is achieved by phase-shift-angle control, and VSC harmonies are eliminated by selective harmonic elimination method (SHEM). VSC has been designed at the highest low-voltage level of 1 kV and connected to a medium-voltage (W) bus through a, low-pass input filter and D...
Citation Formats
O. Erdem and C. F. Bazlamaçcı, “MIPS Extension for a TCAM Based Parallel Architecture for Fast IP Lookup,” presented at the 24th International Symposium on Computer and Information Sciences, Guzelyurt, CYPRUS, 2009, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/53242.