A gate array architecture for high speed correlation and convolution is described. A gate array chip based on this architecture is designed and an FIR filter is implemented on thm chip. Bit-level array in pipeline structure is used in the architecture. For high 1/0 data rate, true single phase clocking circuit technique in CMOS is applied. The gate array chip is designed in 1.2pm CMOS with the programming layer metal-2 only. Spice and Verilog simulations show that the throughput is over 100 MHz


MEMISOGLU, AT; BILGEN, S (1994-04-14)
An adaptive hybrid ARQ scheme for slowly timevarying channels that aims to maximize the average throughput under a given reliability constraint is presented. Punctured convolutional codes and the Viterbi algorithm with the Yamemoto-Itoh retransmission protocol are employed for encoding and decoding, respectively. A procedure based on exponentially weighted moving averages is developed to detect channel state changes
A binomial noised model for cluster validation
Toledano-Kitai, Dvora; Avros, Renata; Volkovich, Zeev; Weber, Gerhard Wilhelm; Yahalom, Orly (IOS Press, 2013-01-01)
Cluster validation is the task of estimating the quality of a given partition of a data set into clusters of similar objects. Normally, a clustering algorithm requires a desired number of clusters as a parameter. We consider the cluster validation problem of determining the optimal ("true") number of clusters. We adopt the stability testing approach, according to which, repeated applications of a given clustering algorithm provide similar results when the specified number of clusters is correct. To implemen...
A state prediction scheme for discrete time nonlinear dynamic systems
Demirbaş, Kerim (Informa UK Limited, 2007-01-01)
A state prediction scheme is proposed for discrete time nonlinear dynamic systems with non-Gaussian disturbance and observation noises. This scheme is based upon quantization, multiple hypothesis testing, and dynamic programming. Dynamic models of the proposed scheme are as general as dynamic models of particle predictors, whereas the nonlinear models of the extended Kalman (EK) predictor are linear with respect to the disturbance and observation noises. The performance of the proposed scheme is compared wi...
A shared-medium communication architecture for distributed discrete event systems
Schmidt, Klaus Verner; Zaddach, J. (2007-06-29)
Recently, several efficient supervisor synthesis approaches for distributed discrete event systems (DES) have been established. In this paper, the implementation of such supervisors on interacting distributed programmable logic controllers (PLCs) on a network is considered for the hierarchical and decentralized control approach elaborated in our previous work. A communication model that captures the controller behavior relevant for communication is developed, and a network architecture together with a sched...
Observability Through a Matrix-Weighted Graph
Tuna, Sezai Emre (Institute of Electrical and Electronics Engineers (IEEE), 2018-07-01)
Observability of an array of identical linear time-invariant systems with incommensurable output matrices is studied, where an array is called observable when identically zero relative outputs imply synchronized solutions for the individual systems. It is shown that the observability of an array is equivalent to the connectivity of its interconnection graph, whose edges are assigned matrix weights. Moreover, to better understand the relative behavior of distant units, pairwise observability that concerns wi...
Citation Formats
I. UNGAN and M. ASKAR, “A GATE ARRAY CHIP FOR HIGH-FREQUENCY DSP APPLICATIONS,” 1994, p. 549, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/65514.