A GATE ARRAY CHIP FOR HIGH-FREQUENCY DSP APPLICATIONS

Date

1994-04-14

Author

UNGAN, IE
ASKAR, M

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A gate array architecture for high speed correlation and convolution is described. A gate array chip based on this architecture is designed and an FIR filter is implemented on thm chip. Bit-level array in pipeline structure is used in the architecture. For high 1/0 data rate, true single phase clocking circuit technique in CMOS is applied. The gate array chip is designed in 1.2pm CMOS with the programming layer metal-2 only. Spice and Verilog simulations show that the throughput is over 100 MHz

Subject Keywords

Automation & Control Systems, Computer Science, Artificial Intelligence, Engineering, Electrical & Electronic, Telecommunications

URI

https://hdl.handle.net/11511/65514

Collections

Department of Electrical and Electronics Engineering, Conference / Seminar

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Citation Formats

I. UNGAN and M. ASKAR, “A GATE ARRAY CHIP FOR HIGH-FREQUENCY DSP APPLICATIONS,” 1994, p. 549, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/65514.