DESIGN, IMPLEMENTATION AND VERIFICATION OF A HIGH-SPEED ON-CHIP PACKET SWITCH

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2022-2-9

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YILDIZ, Ayhan Sefa

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In this thesis, an on-chip packet switch architecture to interconnect modules on System on Chip (SoC) platforms at high line speeds is proposed. The particular target application for the proposed on-chip switch is hardware accelerated cloud computing systems. To this end, FPGA Accelerator Cards (FAC) are employed in heterogeneous cloud data centers which implement hardware accelerators on the FPGA. The data from the cloud user is brought on the accelerators and delivered after processing through high-speed Ethernet Interfaces on the FAC. The FPGA has other modules such as memory modules and SoC processor for supporting the cloud services. To this end, a high-throughput on-chip packet switch is required to interconnect heterogeneous interfaces. Furthermore, the switch design should be scalable and configurable to meet the dynamically changing demands of the cloud data center. The contributions of this thesis are the design, verification and evaluation of an on-chip packet switch that addresses these requirements. The switch is an input-queued switch that operates at line rate to support scalability. The number of ports, the data width and buffer sizes are parametrized and configurable. To the best of our knowledge, there is no on-chip switch implementation presented together with its systematic verification. The on-chip switch design is implemented on the XC7Z100FFG1156-2 SoC of the Xilinx Zynq-7000 family. The pipelined hardware architecture and the memory organization are described in detail. The systematic verification is carried out using the SystemVerilog infrastructure. We demonstrate that the switch supports 100\% throughput at 40 Gbps line speed and a maximum latency around 1250 ns by making use of the statistics collected by SystemVerilog in Modelsim tool.

Subject Keywords

On-chip switch, Switch fabric arbitration, Cloud computing, Verification, Coverage

URI

https://hdl.handle.net/11511/96378

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Graduate School of Natural and Applied Sciences, Thesis

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Citation Formats

A. S. YILDIZ, “DESIGN, IMPLEMENTATION AND VERIFICATION OF A HIGH-SPEED ON-CHIP PACKET SWITCH,” M.S. - Master of Science, Middle East Technical University, 2022.