DESIGN, IMPLEMENTATION AND VERIFICATION OF A HIGH-SPEED ON-CHIP PACKET SWITCH

Download

10450908.pdf

Date

2022-2-9

Author

YILDIZ, Ayhan Sefa

Metadata

Show full item record

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Item Usage Stats

301
views

229
downloads

In this thesis, an on-chip packet switch architecture to interconnect modules on System on Chip (SoC) platforms at high line speeds is proposed. The particular target application for the proposed on-chip switch is hardware accelerated cloud computing systems. To this end, FPGA Accelerator Cards (FAC) are employed in heterogeneous cloud data centers which implement hardware accelerators on the FPGA. The data from the cloud user is brought on the accelerators and delivered after processing through high-speed Ethernet Interfaces on the FAC. The FPGA has other modules such as memory modules and SoC processor for supporting the cloud services. To this end, a high-throughput on-chip packet switch is required to interconnect heterogeneous interfaces. Furthermore, the switch design should be scalable and configurable to meet the dynamically changing demands of the cloud data center. The contributions of this thesis are the design, verification and evaluation of an on-chip packet switch that addresses these requirements. The switch is an input-queued switch that operates at line rate to support scalability. The number of ports, the data width and buffer sizes are parametrized and configurable. To the best of our knowledge, there is no on-chip switch implementation presented together with its systematic verification. The on-chip switch design is implemented on the XC7Z100FFG1156-2 SoC of the Xilinx Zynq-7000 family. The pipelined hardware architecture and the memory organization are described in detail. The systematic verification is carried out using the SystemVerilog infrastructure. We demonstrate that the switch supports 100\% throughput at 40 Gbps line speed and a maximum latency around 1250 ns by making use of the statistics collected by SystemVerilog in Modelsim tool.

Subject Keywords

On-chip switch, Switch fabric arbitration, Cloud computing, Verification, Coverage

URI

https://hdl.handle.net/11511/96378

Collections

Graduate School of Natural and Applied Sciences, Thesis

Suggestions

OpenMETU
Core

A NOVEL FLEXIBLE ON-CHIP SWITCH ARCHITECTURE FOR RECONFIGURABLE HARDWARE ACCELERATORS Yazıcı, Fatih; Schmidt, Şenan Ece; Department of Electrical and Electronics Engineering (2021-8-13) This thesis work proposes ReFlex Switch, a novel, scalable on-chip packet switch architecture, that is designed to interconnect heterogeneous IP cores at high speeds. One target application for ReFlex switch is hardware accelerated cloud computing where the cloud servers feature FPGA cards with reconfigurable regions to implement accelerators demanded by the users. In this setting, the increasing data rates call for line-speed operation of the on-chip switch to maintain scalability. The first requirement o...
An On-chip Switch Architecture for Hardware Accelerated Cloud Computing Systems Donanim Hizlandiricili Bulut Bilisim Sistemleri icin Yonga-ustu Anahtar Mimarisi Yazıcı, Fatih; Yildiz, Ayhan Sefa; Yazar, Alper; Schmidt, Şenan Ece (2020-10-05) © 2020 IEEE.In this paper, we propose a scalable on-chip packet switch architecture for hardware accelerated cloud computing systems. Our proposed switch architecture is implemented on the FPGA and interconnects reconfigurable regions, 40 Gbps Ethernet interfaces and a PCIe interface. The switch fabric operates at line speed to achieve scalability. We propose a new algorithm that grants access to the fabric according to the allocated prioritization to input-output port pairs. The switch is implemented on Xi...
Experimental Analysis and FPGA Implementation of the Real Valued Time Delay Neural Network Based Digital Predistortion Yesil, Soner; Sen, Cansu; Yılmaz, Ali Özgür (2019-01-01) This paper presents an FPGA implementation of the Real Valued Time Delay Neural Network (RVTDNN) based digital predistortion with a very low resource utilization and high throughput. The implementation exploits efficient utilization of FPGA primitives and approximation of activation functions that can be realized with simple logic operations. The proposed modifications and constraints on the algorithms have been decided and verified based on a closed-loop adaptive hardware setup including RFHIC RWP03040-1H ...
Feasibility study for dynamic context switching inpartially reconfigurable FPGAS Yılmaz, Esat; Bazlamaçcı, Cüneyt Fehmi; Department of Electrical and Electronics Engineering (2019) Reconfiguration of computing and control circuits according to dynamically changing needs is a supportive concept which saves design-time and the space needed for floorplanning in comparison to application specific integrated circuits (ASIC). FPGAs which are commonly used reconfigurable devices have both full and partial reconfiguration features. Dynamic partial reconfiguration is a technique which enables some part of the circuit to be reconfigured while other parts are running. This feature allows the use...
Digital control of universal telecommunication power supplies using dual 8-bit microcontrollers Kutluay, K; Cadirci, I; Yafavi, A; Cadirci, Y (2002-10-18) Design and implementation of a digital controller for universal telecommunication power supply modules are presented. The paper emphasises on converter control strategy, and its implementation by means of parallel operated, dual 8-bit microcontrollers. One of the microcontrollers is employed for user interface purposes, such as long term records, display and alarm facilities, which are inherently slow processes. The fast processing speed required by output voltage setting, current limit, and load current sh...

Citation Formats

A. S. YILDIZ, “DESIGN, IMPLEMENTATION AND VERIFICATION OF A HIGH-SPEED ON-CHIP PACKET SWITCH,” M.S. - Master of Science, Middle East Technical University, 2022.