Date

2022-8-11

Author

Beyenir, Aycan

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This thesis presents a new column-parallel analog to digital converter (ADC) integrated circuit with high precision (20-bit), high signal-to-noise ratio (119.5 dB), low power incremental Zoom ADC architecture and demonstrates its integration to a 384x288 pixel format analog output microbolometer readout integrated circuit (ROIC) with 25µm pixel pitch. The Zoom ADC is a hybrid of a low-resolution successive approximation register (SAR) ADC and a high-resolution Delta-Sigma ADC. The main aim of this design is to decrease the power consumption and oversampling ratio (OSR) of the ADC while preserving the high resolution. The designed Zoom ADC consists of a 5-bit SAR ADC, a second-order Delta-Sigma Modulator, and digital filters. The SAR ADC performs the coarse conversion and defines the most significant bits (MSBs), while the Delta-Sigma Modulator performs fine conversion to the residue voltage from the SAR ADC. Digital filters eliminate high-frequency noises and convert modulated data to parallel outputs. These three blocks and column readout circuits vi work with a pipeline chain, increasing sampling rate and decreasing the power consumption. The ADC has a programmable digital filter; thus, the ADC can work with different frame rates and resolutions. The designed ADC has four operation modes: the 20 FPS high-resolution mode, 30 FPS standard mode, 50 FPS fast mode, and 200 FPS ultrafast mode. The ADC design is implemented in a standard 0.18µm CMOS technology. The ADC has 400 columns with a 50 µm pixel pitch, where a single column of the ADC has a 2.4 mm height and covers a 0.12 mm2 area. The ADC provides a 124.5 dB dynamic range (DR) and a 122 dB signal-to-noise ratio (SNR) in the high-resolution mode. The effective number of bits (ENOB) is 20.1, and the DNL is below 0.5 least significant bit (LSB). The sampling rate is 6KS/sec, and the ADC consumes 358 µW power. The ADC can be programmed to reach sampling speed up to 60KS/sec for high frames per second (FPS) imaging, called ultrafast mode. The ADC provides 99.2 dB dynamic range (DR) and 98 dB signal-to-noise ratio (SNR) in the 200 FPS ultrafast mode, where the effective number of bits (ENOB) reduces to 16.1 and the power consumption increases to 751 µW.

Subject Keywords

Analog to Digital Converter, Zoom ADC, Delta-Sigma ADC, Uncooled imaging, Readout Integrated Circuit

URI

https://hdl.handle.net/11511/98677

Collections

Graduate School of Natural and Applied Sciences, Thesis