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A Low-power capacitive integrated CMOS readout circuitry for high performance MEMS accelerometers

İncedere, Osman Samet
This thesis presents a low power capacitive integrated CMOS readout circuitry for high performance MEMS accelerometers. It proposes a linearized model of the complete closed loop accelerometer system, which makes easier of designing and analyzing the system. Designed readout circuitry offers low noise, wide dynamic range and high linearity system with very low power consumption. Designed readout circuit includes proportional integral (PI) controller circuit, which significantly decreases the proof mass deflection of the accelerometer resulting in high linearity and high immunity to sensor parameter changes. Designed system also suppresses the readout circuit noise in a significant amount and this noise suppression allows designing very low power readout circuits without degrading the noise performance of the system. Readout circuit provides highly programmable digital controller circuit, which allows controlling of all digital timing signals, bias currents and voltages, and power consumptions of analog blocks, front-end circuit gain, gain coefficients of PI controller and sigma-delta modulator gain. Designed readout circuit also offers optional external timing signals and optional external voltage reference. The readout circuit is implemented using 0.35 um process. Circuit level and system level simulations are performed in Cadence and MATLAB Simulink environments respectively. The simulations guarantee stability and proper operation of the accelerometer system. As a sensing element, accelerometer having the ! v! specifications of 3.5x10-6 F/m sensitivity, 9.5 pF rest capacitance, 2.32 kHz resonant frequency and 4.6 μg/√Hz Brownian noise, is used. Simulation results show that system has 5.3 μg/√Hz noise level at the output, ± 19.5 g full scale range, 128.5 dB dynamic range and 1.8 mW power consumption with 3.3 V supply voltage.