PARTIAL RECONFIGURATION ON A REAL-TIME TARGET DETECTION AND TRACKING SYSTEM

2014-04-25
Tengilimoglu, Bengisu
Bazlamaçcı, Cüneyt Fehmi
The concept of partial reconfiguration has been introduced by leading FPGA vendors in recent years. Partial reconfiguration is a technique that allows to reprogram/reconfigure a specific part of an FPGA during run-time. This method allows switching between design modules that are not necessary to function at the same time without interrupting the FPGA's processing of the current task Hence larger designs can be implemented on the same FPGA. This work is an implementation of partial reconfiguration on an FPGA which is used as a hardware accelarator in a real-time target detection and tracking system. Run-time switching between different algorithm components became possible without interrupting the target detection and tracking capability of the overall system by using partial reconfiguration in the system. By this approach, FPGA resources are used efficiently and power consumption is reduced.

Suggestions

Efficient Abstractions for the Supervisory Control of Modular Discrete Event Systems
Schmidt, Klaus Verner (2012-12-01)
The topic of this technical note is the nonblocking and maximally permissive abstraction-based supervisory control for modular discrete event systems (DES). It is shown, that an efficient abstraction technique, that was developed for the nonconflict verification of modular DES, is also suitable for the nonblocking supervisory control. Moreover, it is proved that this abstraction technique can be extended by the condition of local control consistency, in order to achieve maximally permissive supervision. Dif...
FASST: A high performance scalable rule table hardware architecture for software defined networks-FASST: Yazılım Tanımlı Bilgisayar Agları içinYüksek Ba¸sarımlı, Ölçeklenebilir bir Kural TablosuDonanım Mimarisi
ERAL, GÖKSAN; Schmidt, Şenan Ece (2018-07-09)
In this paper, a new hardware architecture FASST, which can provide high performance in packet classification for SDN Rule Tables, is proposed. FASST achieves high throughput at very low packet latency using a TCAM-based parallel cache, temporal locality in the network and FPGA hardware parallelism. FASST is implemented and evaluated on Altera Stratix-V FPGA and 200 M packets/s throughput is verified functionally. FASST achieves a significantly lower average packet latency by exploiting the strong temporal ...
A low latency, high throughput and scalable hardware architecture for flow tables in software defined networks
Eral, Göksan; Schmidt, Şenan Ece; Department of Electrical and Electronics Engineering (2016)
Software Defined Networking (SDN) is a new paradigm which requires multi-field packet classification for each received packet by looking up Flow Tables which contain a large number of rules and corresponding actions. The rules are defined by upto 15 packet header fields including IP source and destination address. If more than one rule rule matches then the action of the highest priority rule is executed. Furthermore rules with wildcard fields are possible. The SDN Flow Table should scale with the rule coun...
Controller synthesis for an I/O-based hierarchical system architecture
Perk, Sebastian; Moor, Thomas; Schmidt, Klaus Verner (2008-10-08)
In our previous work, a framework for the hierarchical design of discrete event systems has been introduced that is based on a notion of inputs and outputs. I/O-plant models describe the interaction of each subsystem with the operator (or controller) and the environment. By alternation of subsystem composition and controller synthesis, a hierarchy of controllers is obtained that complements a hierarchy of environment models. An admissibility condition was presented that implies liveness while allowing for a...
Hardware Accelerators for Cloud Computing: Features and Implementation
Tirlioglu, Anil; Demir, Omer Bayram; Yazar, Alper; Schmidt, Şenan Ece (2021-01-01)
In this paper, hardware accelerator (FHA) applications realized on FPGA that can be offered as a service in cloud computing systems are discussed. It is necessary to know the hardware resources used by FHA applications and the performance they provide for the efficient meeting of the user requests and effective resource planning. To this end, the first contribution of this paper is to provide a compilation of the literature on the features of frequently used hardware accelerators (matrix multiplication, fac...
Citation Formats
B. Tengilimoglu and C. F. Bazlamaçcı, “PARTIAL RECONFIGURATION ON A REAL-TIME TARGET DETECTION AND TRACKING SYSTEM,” 2014, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/52628.